1. general description the npic6c596a-q100 is an 8-bit serial-in/se rial or parallel-out shift register with a storage register and open-drain outputs. both the shift and storage register have separate clocks. the device features a serial input (ds) and a serial output (q7s) to enable cascading and an asynchronous reset mr input. a low on mr resets both the shift register and storage register. data is shifte d on the low-to-high transitions of the shcp input. the data in the shift register is transferred to the storage register on a low-to-high transition of the stcp input. if both clocks are connected together, the shift register is always one clock pulse ahead of the storage register. to provide additional hold time in cascaded applications, the serial outpu t qs7 is clocked out on the falling edge of shcp. data in the storage register drives the gate of the output extended-drain nmos (ednmos) transistor whenever the output enable input (oe ) is low. a high on oe causes the outputs to assume a high-im pedance off-state. operation of the oe input does not affect the state of the registers. the open-drain outputs are 33 v/100 ma continuous current extended-drain nmos transistors designed for use in systems that require moderate load power such as leds. integrated voltage clamps in the outputs, provide protection against in ductive transients. these voltage clamps make the device suitable for power driver applications such as relays , solenoids and other low-current or medium-voltage loads. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? wide supply range 2.3 v to 5.5 v ? low r dson ? eight power ednmos transistor outputs of 100 ma continuous current ? 250 ma current limit capability ? output clamping voltage 33 v ? 30 mj avalanche energy capability ? enhanced cascading for multiple stages ? all registers cleared with single input ? low power consumption ? esd protection: ? hbm aec-q100-002 revision d exceeds 2500 v ? cdm aec-q100-011 revision b exceeds 1000 v npic6c596a-q100 power logic 8-bit shift re gister; open-drain outputs rev. 1 ? 18 october 2013 product data sheet
npic6c596a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 18 october 2013 2 of 20 nxp semiconductors npic6c596a-q100 power logic 8-bit shift register; open-drain outputs 3. applications ? led sign ? graphic status panel ? fault status indicator 4. ordering information 5. functional diagram table 1. ordering information type number package temperature range name description version npic6c596ad-q100 ? 40 ? cto+125 ? c so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 npic6c596apw-q100 ? 40 ? cto+125 ? c tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 NPIC6C596ABQ-Q100 ? 40 ? cto+125 ? c dhvqfn16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 ? 3.5 ? 0.85 mm sot763-1 fig 1. logic symbol fig 2. functional diagram q0 ds shcp mr stcp q1 3 15 10 2 4 5 6 11 12 13 14 9 78 q2 q3 q4 q5 q6 q7 q7s oe aaa-002547 3 q0 4 q1 5 q2 6 q3 open-drain outputs 8-bit storage register 8-stage shift register 11 q4 12 q5 13 q6 14 q7 oe stcp mr shcp q7s ds 2 15 9 7 10 8 aaa-002548
npic6c596a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 18 october 2013 3 of 20 nxp semiconductors npic6c596a-q100 power logic 8-bit shift register; open-drain outputs fig 3. schematic of all inputs fig 4. schematic of open-drain outputs (qn) aaa-002550 gnd v cc aaa-002551 gnd qn 33 v fig 5. logic diagram d d d * 1 ' 4 ' ' 4 4 4 6 4 6 7 $ * ( 6 6 7 $ * ( 6 7 $ * ( 7 2 6 7 $ * ( & |